Flip-flop circuit

Abstract

PURPOSE:To reduce the pattern occupying area against high speed by inputting directly a control signal of set/reset to a gate of a feedback circuit so as to eliminate the effect on the circuit operation when set/reset is not in operation. CONSTITUTION:A transistor (TR) 27 is turned on when a set terminal is at ''1'', an output Q' is goes forcibly to ''0'' and an output Q goes forcibly to ''1''. On the other hand, a TR22 is turned on and the TR27 is turned off when the set terminal is at ''0''. As a load to the output Q' line, a gate capacitance of an inverter 21 is small. The junction capacitance of a feedback loop of a block 28 can be small, because the junction capacitance of the TR27 only is large. Thus, the load capacitance of the Q' line is small, the clock inverter 2 is speeded up. Since only the dimension of a few TRs has only to be increased against the high speed of the circuit operation, an FF circuit having a small pattern occupying area is obtained.

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Patent Citations (1)

    Publication numberPublication dateAssigneeTitle
    JP-S5579524-AJune 16, 1980Fujitsu LtdFlip-flop circuit

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Cited By (2)

    Publication numberPublication dateAssigneeTitle
    JP-2008167292-AJuly 17, 2008Fujitsu Ltd, 富士通株式会社Latch circuit, flip-flop circuit with the same and logic circuit
    JP-2014155163-AAugust 25, 2014Toshiba Corp, 株式会社東芝フリップフロップ回路